Device structure and electrical characteristics of strained-Si-on-insulator (strained-SOI) MOSFETs

Strained-Si CMOS is an attractive device structure to be able to relax several fundamental limitations of CMOS scaling, because of high electron and hole mobility and compatibility with Si CMOS standard processing. In this paper, we present a new device structure including strained-Si channel, strained-SOI MOSFET, applicable to CMOS under sub-100 nm technology nodes. The main feature of this device is that thin strained-Si channel/relaxed SiGe heterostructures are formed on buried oxides. The principle and the advantages are described in detail. The strained-SOI structure has been successfully fabricated by combining the SIMOX technology with regrowth of strained Si films. It is demonstrated that strained-SOI n- and p-channel MOSFETs have mobilities 1.6 and 1.3 times higher than conventional Si MOSFETs, respectively. We also present a novel technique for fabricating ultra-thin SiGe-on-insulator (SGOI) virtual substrates with high Ge content by high temperature oxidation of SGOI with lower Ge content. A 16-nm-SGOI substrate having a Ge content as high as 57% has been successfully fabricated.