Mobility-limiting mechanisms in single and dual channel strained Si/SiGe MOSFETs

Dual channel strained Si/SiGe CMOS architectures currently receive great attention due to maximum performance benefits being predicted for both n- and p-channel MOSFETs. Epitaxial growth of a compressively strained SiGe layer followed by tensile strained Si can create a high mobility buried hole channel and a high mobility surface electron channel on a single relaxed SiGe virtual substrate. However, dual channel n-MOSFETs fabricated using a high thermal budget exhibit compromised mobility enhancements compared with single channel devices, in which both electron and hole channels form in strained Si. This paper investigates the mobility-limiting mechanisms of dual channel structures. The first evidence of increased interface roughness due to the introduction of compressively strained SiGe below the tensile strained Si channel is presented. Interface corrugations degrade electron mobility in the strained Si. Roughness measurements have been carried out using AFM and TEM. Filtering AFM images allowed roughness at wavelengths pertinent to carrier transport to be studied and the results are in agreement with electrical data. Furthermore, the first comparison of strain measurements in the surface channels of single and dual channel architectures is presented. Raman spectroscopy has been used to study channel strain both before and after processing and indicates that there is no impact of the buried SiGe layer on surface macrostrain. The results provide further evidence that the improved performance of the single channel devices fabricated using a high thermal budget arises from improved surface roughness and reduced Ge diffusion into the Si channel.