Impact of large angle tilt implantation on the threshold voltages of LDMOS transistors on SOI

A purely vertical (0°) implantation and a large-angle tilt implantation (LATID) (usually 45°) are used to form the short channel of an LDMOS transistor. A modelling of both implantations is first carried on taking into account the geometrical effects of the LATID as well as the strong channelling of the vertical implantation. Based on this accurate modelling of the doping regions, the threshold voltage of an 8 nm gate-oxide n-LDMOS transistor on silicon-on-insulator (SOI) in the advanced bipolar CMOS–DMOS (ABCD) technology is calculated and successfully compared with experiment. An optimization is then carried on for a new generation of 7 nm-gate-oxide LDMOS. This transistor suffers from a degradation of the threshold voltage because of modified channel conditions such as the length and peak concentration due to the thinner gate-oxide. The impact of temperature, implantation energy and tilt angle are simulated and the threshold voltage is adjusted by device simulations. It is found that the impact of LATID implantation is important on the channel condition which links directly to the threshold voltage. A 60° tilt with some LATID dose modifications gives very good optimization. A comparison of the two gate-oxide thicknesses with the optimized channel condition is shown at last.