Technology CAD of silicided Schottky barrier MOSFET for elevated source–drain engineering

Technology CAD has been used to study the performance of a silicided Schottky barrier (SB) MOSFET with gate, source and drain contacts realized with nickel-silicide. Elevated source–drain structures have been used towards the S/D engineering of CMOS devices. A full process-to-device simulation has been employed to predict the performance of sub-micron SB n-MOSFETs for the first time. A model for the diffusion and alloy growth kinetics has been incorporated in SILVACO–ATLAS and ATHENA to explore the processing and design parameter space for the Ni-silicided MOSFETs. The temperature and concentration dependent diffusion model for NiSi have been developed and necessary material parameters for nickel-silicide and epitaxial-Si have been incorporated through the C-interpreter function. Two-dimensional (2D) process-to-device simulations have also been used to study the dc and ac (RF) performance of silicided Schottky barrier (SB) n-MOSFETs. tracted sheet resistivity, as a function of annealing temperature of the silicided S/D contacts, is found to be lower than the conventional contacts currently in use. It is also shown that the Technology CAD has the full capability to predict the possible dc and ac performance enhancement of a MOSFET with elevated S/D structures. While the simulated dc performance shows a clear enhancement, the RF analyses show no performance degradation in the cut-off frequency/propagation delay and also improve the ac performance due to the incorporation of silicide contacts in the S/D region.