Novel enhanced stressors with graded encapsulated SiGe embedded in the source and drain areas

An advanced CMOS scheme for the integration of a graded epitaxial Silicon Germanium (SiGe) layer is presented. SiGe is deposited into the source drain regions right after gate formation to create compressive strain in the transistor channel of the pMOSFETs and thus improve charge carrier mobility. The SiGe layer is exposed to subsequent process steps such as cleaning, implantation and annealing which cause erosion and dopant loss. This effect becomes more severe with increasing Ge content, which is wanted to increase stress in the channel. The negative effect of SiGe erosion on DC transistor performance is shown in this paper and how it can be reduced by optimized SiGe deposition utilizing a two layer stack with different Ge content. First a film with higher Ge concentration is deposited followed by a lower percent Ge film which is aimed to protect the SiGe film underneath. Electrical data for PMOS devices with 55 nm embedded SiGe with 20–30% Ge are presented and compared to the corresponding graded SiGe stack (25–30%, 50 nm with 5 nm thick 15% cap). Comparing Embedded Silicon Germanium (eSiGe) devices with 30 at% Ge, we see a 5% IDSAT improvement for the graded layer over the monolithic one.