Author/Authors :
Panebianco، نويسنده , , S and Lo Presti، نويسنده , , D and Russo، نويسنده , , G.V and Caponetto، نويسنده , , C and Petta، نويسنده , , C and Randazzo، نويسنده , , N and Reito، نويسنده , , S and Russo، نويسنده , , M، نويسنده ,
Abstract :
We present the design and the test performed on ADeLinel, a Full-Custom Analog Memory for sparse data sampling. It has been designed as an array of switched capacitors. It is only one channel of 8 cells. The control part of the ADeLine chip is custom designed for the size reduction, high speed performance and low power dissipation. The memory has been integrated in double poly, double metal AMS 0.8 μm CMOS. It has 3.5 V input and output swings, a linearity within ± 6 mV in a 2 V range and 11 bits of resolution.
