64-Channel, 5 GSPS ADC Module with Switched Capacitor Arrays

We present a 5 GSPS ADC/Data processing module with up to 64 channels and 2048 cells per channel, designed for fast-sampling, front-end applications. This is a 6U VME board that incorporates 16 pieces DRS4 (http://drs.web.psi.ch, [1]) Switched Capacitor Array chips developed at Paul Scherrer Institut, Switzerland. The 16 DRS4 chips are grouped in four independent input blocks. A block, with a geometric size of 43×120 mm, has four pieces DRS4 chips, four pieces AD9222 converters, and one Altera Stratix III FPGA. Each DRS4 chip has eight channels and each channel has 1024 sampling cells, which can be daisy-chained for larger sampling depth. This feature allows for a great level of flexibility in choosing the number of channels relative to capacitor array size, for a particular application. The first prototype Printed Circuit Board (PCB) was designed for a sampling depth of 2048 cells and 16 channels in a 42 mm wide block, i.e. 64 channels for the 6U VME board. This compact form factor allows for these input blocks to be used as front-end electronics for the Cherenkov Telescope Array (CTA) cameras. In this VME board, the four blocks are fully independent and can run each in different modes without any conflict. A global FPGA, also a Stratix III device, provides control and interfacing. The module can run with a local oscillator or with input system clocks in the range of 20–550 MHz. The front panel is fitted with a 2.5 Gbps serial link transceiver.