Title of article
A fast readout algorithm for Cluster Counting/Timing drift chambers on a FPGA board
Author/Authors
Cappelli، نويسنده , , L. and Creti، نويسنده , , P. and Grancagnolo، نويسنده , , F. and Pepino، نويسنده , , A. and Tassielli، نويسنده , , G.، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2013
Pages
3
From page
226
To page
228
Abstract
A fast readout algorithm for Cluster Counting and Timing purposes has been implemented and tested on a Virtex 6 core FPGA board. The algorithm analyses and stores data coming from a Helium based drift tube instrumented by 1 GSPS fADC and represents the outcome of balancing between cluster identification efficiency and high speed performance. The algorithm can be implemented in electronics boards serving multiple fADC channels as an online preprocessing stage for drift chamber signals.
Keywords
Front-end electronics , Cluster Counting/Timing , FPGA , Drift chambers , fADC
Journal title
Nuclear Instruments and Methods in Physics Research Section A
Serial Year
2013
Journal title
Nuclear Instruments and Methods in Physics Research Section A
Record number
2194186
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