KPIX: a pixel detector imaging chip

We present a VLSI custom device, named KPIX, developed in a 0.6 μm CMOS technology. The circuit is dedicated to readout solid-state detectors covering large areas (on the order of square centimetre) and featuring very small currents. KPIX integrates 1024 channels (current amplifiers) and 8 ADCs on a 15.5×4 mm2 area. Both an analogue and digital readout are allowed, with a 10 bit amplitude resolution. Amplifiers are organized in 8 columns of 128 rows. When choosing the digital or the analogue readout, the complete set of channels can be read out in about 30 ms. The specific design of the amplification cells allows to measure very small input current levels, on the order of fractions of pico-ampere. Power consumption has also been kept at the level of 80 μW per cell and 150 mW (peak value) in total. The specific chip architecture and geometry allow use of many KPIX circuits together in order to serve a large detector sensitive area. The KPIX structure is presented along with some measurements characterizing its performance.