Author/Authors :
Beccherle، نويسنده , , R and Darbo، نويسنده , , G and Gagliardi، نويسنده , , G and Gemme، نويسنده , , C and Morettini، نويسنده , , P and Musico، نويسنده , , P and Osculati، نويسنده , , B and Oppizzi، نويسنده , , P and Pratolongo، نويسنده , , F and Ruscino، نويسنده , , E and Schiavi، نويسنده , , C and Vernocchi، نويسنده , , F and Blanquart، نويسنده , , L and Einsweiler، نويسنده , , K and Meddeler، نويسنده , , G and Richardson، نويسنده , , J and Comes، نويسنده , , G and Fischer، نويسنده , , P and Calvet، نويسنده , , D and Boyd، نويسنده , , R and ???cho، نويسنده , , P، نويسنده ,
Abstract :
In this article we describe the architecture of the Module Controller Chip for the ATLAS Pixel Detector. The project started in 1997 with the definition of the system specifications. A first fully-working rad-soft prototype was designed in 1998, while a radiation hard version was submitted in 2000. The 1998 version was used to build pixel detector modules. Results from those modules and from the simulated performance in ATLAS are reported. In the article we also describe the hardware/software tools developed to test the MCC performance at the LHC event rate.
Keywords :
LHC , ATLAS , Silicon pixel detectors , Radiation hardness , ASIC
