Monte Carlo based time-domain Hspice noise simulation for CSA-CRRC circuit

We present a time-domain Monte Carlo based Hspice noise simulation for a charge-sensitive preamplifier-CRRC (CSA-CRRC) circuit with random amplitude piecewise noise waveform. The amplitude distribution of thermal noise is modeled with Gaussian random number. For 1/f noise, its amplitude distribution is modeled with several low-pass filters with thermal noise generators. These time-domain noise sources are connected in parallel with the drain and source nodes of the CMOS input transistor of CSA. The Hspice simulation of the CSA-CRRC circuit with these noise sources yielded ENC values at the output node of the shaper for thermal and 1/f noise of 47e− and 732e−, respectively. ENC values calculated from the frequency-domain transfer function and its integration are 44e− and 882e−, respectively. The values for Hspice simulation are similar to those for frequency-domain calculation. A test chip was designed and fabricated for this study. The measured ENC value was 904 e−. This study shows that the time-domain noise modeling is valid and the transient Hspice noise simulation can be an effective tool for low-noise circuit design.