CASIS1.0: A prototype VLSI front-end ASIC with ultra-large dynamic range and integrated ADC for silicon calorimetry in space experiments

In the framework of the INFN R&D project CASIS, a 6-channel prototype of an integrated front-end circuit optimized for silicon calorimeters to be used in future astroparticle physics experiments was designed and realized in a CMOS 0.35 μm technology. Five channels feature a double-gain charge sensitive preamplifier with real-time automatic gain selection, a correlated double sampling filter and, for test purposes, a fully differential, 12-bit cyclic ADC. A sixth channel, featuring only the ADC, is also implemented. The circuit design and test results are presented in this paper. The design goals of a linear dynamic range of 104 MIP (50 pC) in “low-gain” mode and a signal-to-noise ratio of 5:1 for single-MIP signals (with an input capacitive load of 300 pF) in “high-gain” mode were achieved.