Heavy ion-induced SEEs on 130 nm CMOS technology for LHC application—status and challenges

This work summarizes the status of the art of electronic designs, using CMOS technologies, to stand LHC and S-LHC radiation-hard environments. Radiation effects can be divided into Single Event Effects and Total Ionizing Dose effects, which are consequences of different interaction effects within the silicon and the electronics. These types of effects are commonly investigated and faced separately. The commercial 130 nm CMOS technology, today primarily proposed for SLHC electronic upgrades, only implements redundancies against the Single Event Effects`. On the contrary, the 250 nm technology node used in the past years for LHC experiments, was also hardened against the Total Ionizing Dose. Hence, the choice of the technology to be used for high-energy experiments is very crucial as it implies huge efforts in the designs of the components. In addition, an unavoidable technology scaling keeps moving toward ever-smaller sizes and this affects the availability of the silicon process for medium and long-term experiments.