3D-vertical integration of sensors and electronics

Technologies are being developed which enable the vertical integration of sensors and electronics as well as multilayer electronic circuits. New thinning and wafer bonding techniques and the formation of small vias between resulting thin layers of electronics enable the design of dense integrated sensor/readout structures. We discuss candidate technologies based on SOI and bulk CMOS. A prototype 3D chip developed at Fermilab that incorporates three tiers of 0.18 μ m CMOS is described.