Nano-scale scratching in chemical–mechanical polishing

During chemical–mechanical polishing (CMP) in the fabrication of advanced semiconductor devices, undesirable nano-scale scratches are produced, especially in the presence of low-k dielectrics. In this paper, the lower- and upper-bound loads for scratching are estimated by contact mechanics models and are validated by AFM experiments. Additionally, the width and depth of scratches are related to such process parameters as: particle size, abrasive volume fraction, mechanical and geometric properties of the pad and surface coatings, and polishing pressure. The upper-limit for scratch width is found to be a function of the particle size and the hardnesses of the coatings and the pad. In Cu CMP this limit is about one-fifth of the abrasive diameter.