Design and Simulation of a Modified 32-bit ROM-based Direct Digital Frequency Synthesizer on FPGA

This paper presents a modified 32-bit ROM-based Direct Digital Frequency Synthesizer (DDFS). Maximum output frequency of the DDFS is limited by the structure of the accumulator used in the DDFS architecture. The hierarchical pipeline accumulator (HPA) presented in this paper has less propagation delay time rather than the conventional structures. Therefore, it results in both higher maximum operating frequency and higher maximum output frequency. Ripple Carry Adder (RCA) is used at each stage of Conventional pipeline accumulators, whereas the modified pipeline technique contains Carry Look-ahead Adder (CLA) instead of RCA. The proposed method consists of hierarchical adders that have three parts, two blocks of 4-bit CLA and a separated block to estimate carry bits independently. To reach a better frequency resolution in the DDFS, larger phase accumulator is needed. Moreover, in conventional DDFSs, as the number of phase bits increases, to have non-truncated phase mapping, huge amount of memory will be needed. The trigonometric relations of the sine and the cosine functions are used in the phase mapping technique proposed by Symon in order to reduce the size of the Look Up Table (LUT). The method applied in this work combines quarter wave symmetry of the sine samples, the phase difference between the sine and the cosine samples and trigonometric relations of the sine and the cosine functions to reduce the total memory size. The SFDR of the output wave will remain approximately constant (132 dBc) in comparison with the previous works. Finally, the proposed architecture is simulated on Stratix II FPGA. This structure has the frequency range of 0 to 245 MHz with 0.05 Hertz frequency resolution.