Device and Circuit Performance Simulation of a New Nano- Scaled Side Contacted Field Effect Diode Structure

A new side-contacted field effect diode (S-FED) structure has been introduced as a modified S-FED, which is composed of a diode and planar double gate MOSFET. In this paper, drain current of modified and conventional S-FEDs were investigated in on-state and off-state. For the conventional S-FED, the potential barrier height between the source and the channel is observed to become larger and the flow of injected electrons is reduced. Thus, the drain current decreases in on-state. While in offstate, the potential barrier height and width become smaller in conventional S-FED and so the drain current is greater than that of modified structure. Mixed mode simulations were used to determine the performance of the proposed logic gates. We compared the operation of modified S-FED with that of conventional S-FED. Simulated power delay product (PDP) of the modified S-FED-based NOR, NAND, XOR gates were found to be about 416fJ, 408fJ and 336fJ, respectively, compared with 906fJ, 810fJ and 705fJ achievable with conventional S-FED logic gates.