Power Reduction of the Low Offset Dynamic Comparator with Novel Techniques

In this paper, dynamic comparators structure, by employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters, have been presented. The proposed comparators have low consumption thanks to power reduction methods. They have the ability for adjusting the offset. The comparators consume 14.3 and 24 μW at 100 MHz, which is equal to 3.7 and 11.8 fJ. The comparators are designed and simulated in 180 nm CMOS. Layouts occupy 210 and 240 μm2, respectively.