Analysis and Design of High Speed 4-2 Compressor in CMOS Technology for High Speed Multipliers

This review paper contains the discussion about performance analysis of high speed 4-2 compressor architectures, starting from the general idea; conventional form for implementation of this building block along with its truth table has been studied. Thereafter, the modified versions which show promise for high speed multiplier implementations along with their benefits and drawbacks were demonstrated and comprehensively analyzed. Following the same principles, an optimized structure for 4-2 compressor is obtained which has 2 XOR gate level delay for the critical path and contains the least delay among the reported works. As another advantage, because of uniform paths the output waveforms will be free of any glitches. Simulation results for TSMC 0.18 µm CMOS technology and 1.8V power supply using HSPICE have been provided to show the superiority of our designed architecture in terms of the speed performance. Finally, to confirm the correct behavior of proposed compressor, an 8x8 bit multiplier was designed which can operate at the frequency of 500MHz without employing any special multiplication algorithm for partial product generation.