Channel thickness dependency of highk gate dielectric based double-gate CMOS inverter

This work investigates the channel thickness dependency of high-k gate dielectric-based complementary metal-oxide-semiconductor (CMOS) inverter circuit built using a conventional double-gate metal gate oxide semiconductor field-effect transistor (DG-MOSFET). It is espied that the use of high-k dielectric as a gate oxide in n/p DG-MOSFET based CMOS inverter results in a high noise margin as well as gain. It is also found that delay performance of the inverter circuit also gets upgraded slightly by using high-k gate dielectric materials. Further, it is observed that the scaling down of channel thickness (T_Si) improves the noise margin (NM), and gain (A) at the cost of propagation delay (Pd). Moreover, it is also observed that the changes in noise margin (ΔNM = NM_(K=40) – NM_(K=3.9)), propagation delay (ΔP_d = P_d (K=40) – P_d (K=3.9)), and gain (ΔA = A_(K=40) – A_(K=3.9)) gets hinder at lower T_Si. Therefore, it is apposite to look at lower channel thickness (~6 nm) while designing high-k gate dielectric-based DG-MOSFET for CMOS inverter cell.