Designing majority gate‑based nanoscale two‑dimensional two‑dot one‑electron parity generator and checker for nano‑communication

At the present time, logic circuits design prototypes with quantum-dot cellular automata (QCA) have been comprehensively researched. The confines of orthodox CMOS technology induce to the breakthroughs of different technologies, one of which is QCA. Thoughtlessly, because of the deficiency of advance assembly support, QCA circuits frequently agonize from several sorts of manufacture shortcomings and variations and, hence, are error prone and defective. QCA technology is forming its aspect due to extreme effectiveness and rapidity with lesser area requirement. This study, a novel architecture of parity generator and checker, is proposed based on two-dot one-electron cells. Parity generator and checker assist in impeccable binary information communication from point to point. With the outlined parity generator and checker circuit, a nano-communication architecture is designed. The designed architecture is rationalized with a competently established standard mathematical operation based on Coulomb’s theory. All the outlined design contains a minimum number of cells, extent, and energy compared to existing four-dot two-electron QCA designs. The outlined designs comprehend minimum majority gate and latency. Besides, power depletion by the designs is measured and it is perceived that the total energy and power required to operate these designs are incredibly low.