Title of article :
A low-memory intensive decoding architecture for double-binary convolutional t u r b o code
Author/Authors :
ZHAN, Ming University of Electronic Science and Technology of China - National Key Laboratory of Science and Technology on Communications, China , ZHAN, Ming Southwest University - School of Electronics and Information Engineering, China , ZHOU, Liang University of Electronic Science and Technology of China - National Key Laboratory of Science and Technology on Communications, China , WU, Jun Waseda University - Global Information and Telecommunication Institute, Japan
Abstract :
Memory accesses take a large part of the power consumption in the iterative decoding of double-binary convolutional turbo code (DB-CTC). To deal with this, a low-memory intensive decoding architecture is proposed for DB-CTC in this paper. The new scheme is based on an improved maximum a posteriori probability algorithm, where instead of storing all of the state metrics, only a part of these state metrics is stored in the state metrics cache (SMC), and the memory size of the SMC is thus reduced by 25%. Owing to a compare-select-recalculate processing (CSRP) module in the proposed decoding architecture, the unstored state metrics are recalculated by simple operations, while maintaining near optimal decoding performance.
Keywords :
Branch metrics , computational complexity , MAP algorithm , state metrics cache
Journal title :
Turkish Journal of Electrical Engineering and Computer Sciences
Journal title :
Turkish Journal of Electrical Engineering and Computer Sciences
