A 5-bit 5 Gs/s ash ADC using multiplexer-based decoder

This paper presents a 5-bit ash analog-to-digital converter design using the 0.18-µm Taiwan Semiconductor Manufacturing Company s CMOS technology library. The designed system consists of 2 main blocks, a comparator array, and a digital decoder. The digital decoder contains a latch, 1-of-N decoder, and fat-tree encoder units. The 1-of-N decoder is implemented using 2 χ 1 multiplexers. As a result, the active die area and the power consumption are reduced, in addition to an increase in the sampling frequency. The power supply voltage range for the overall system is 0.9 V. For testing purposes, a ramp signal of between -0.45 V and 0.7 V is applied to the converter input. The sampling frequency is 5 Gs/s. The simulation results include a maximum power consumption of 28 mW, integral nonlinearity values of between {0.65 least significant bits (LSB) and +0.01 LSB, differential nonlinearity values of between -0.3 LSB and +0.13 LSB, and an active die area of 0.1 mm^2 .