Author/Authors :
WANG, Xin University of California - Department of Electrical Engineering, USA , FAN, Siqiang Freescale Semiconductor Inc., USA , ZHAO, Hui University of California - Department of Electrical Engineering, USA , LIN, Lin University of California - Department of Electrical Engineering, USA , FANG, Qiang University of California - Department of Electrical Engineering, USA , TANG, He University of California - Department of Electrical Engineering, USA , WANG, Albert University of California - Department of Electrical Engineering, USA
Abstract :
As integrated circuits (IC) technologies advance into very-deep-sub-micron (VDSM), electrostatic discharge (ESD) failure becomes one of the most devastating IC reliability problems and on-chip ESD protection design emerges as a major challenge to radio frequency (RF), analog, and mixed-signal (AMS) IC designs. This paper reviews key design aspects and recent advances in whole-chip ESD protection designs for RF/AMS IC applications in CMOS technologies.
Keywords :
electrostatic discharge (ESD) , ESD protection , radio frequency (RF) , parasitic capacitance
