Author/Authors :
CHEN, Guang On Semiconductor, USA , WANG, Xin University of California - Department of Electrical Engineering, USA , FAN, Siqiang Freescale Semiconductor Inc., USA , TANG, He University of California - Department of Electrical Engineering, USA , LIN, Lin University of California - Department of Electrical Engineering, USA , WANG, Albert University of California - Department of Electrical Engineering, USA
Abstract :
Electrostatic discharge (ESD) induced parasitic effects have serious impacts on performance of radio frequency (RF) integrated circuits (IC). This paper discusses a comprehensive noise analysis procedure for ESD protection structures and their negative influences on RF ICs. Noise figures (NFs) of commonly used ESD protection structures and their impacts on a single-chip 5.5 GHz low-noise amplifier (LNA)circuit were depicted. A design example in 0.18 μm SiGe BiCMOS was presented. Measurement results confirm that significant noise degradation occurs in the LNA circuit due to ESD-induced noise effects. A practical design procedure for ESD-protected RF ICs is provided for real-world RF IC optimization.
Keywords :
electrostatic discharge (ESD) protection , low , noise amplifier (LNA) , noise figures (NFs) , radio frequency (RF) , integrated circuits (IC)
