Design and Evaluation of an Input Buffered Packet Switch

Many architectures of internet routers, ATM and ethernet switches have been proposed and analysed in literature. Theoretically reliable and valid solutions have been developed to achieve high performances but a lot of them are not feasible in practice for commercial and technological reasons. Few papers develop the implementation and simulation aspects. The objective of this paper is the design of a packet switch with a minimum cost and hardware complexity. We propose an input-queuing architecture using a multistage interconnection network and a simple cell selection policy implemented by hardware. The switch is described and simulated using a VHDL language. Performances in terms of throughput and cell loss are evaluated.