Evolutionary QCA Universal and Testable Gate

Quantum-dot Cellular Automata (QCA) with properties such as high density and low power consumption is a promising technology for VLSI future. But high error rate is a disadvantage of this technology, hence it is necessary to design circuits with testability. In this paper a new universal and testable 3×3 gate is designed.This gate is a kind of intelligent systems; because the possible system error can be distinguished by the output values. This gate is designed in a way that it has always 2 ones and one zero in its outputs. When the gate works properly the majority of the outputs must be one and the logical an‎d operation of the outputs must be zero. Thus in the presence of any transient and permanent fault such as single missing cell the majority and an‎d of the outputs are not equal to those in fault free operation. Then the performance of this gate is compared with useful testable Fredkin gate and is shown that for implementing logic functions this gate has a better performance in terms of complexity and delay in comparison with Fredkin gate.