The Impact of Excess-Modulo Representation of Residues on Modulo-(2^n - 5 ) Parallel Prefix Addition

It is desirable to realize latency-balanced computation channels in residue number systems (RNS). In particular modulo-(2^n -δ) addition with selected values of δ (e.g., δ ϵ {1,3,5}) is of interest. Modulo-(2^n - 1 ) adders are realized via one s complement addition, where (2^n - 1 ) is also valid as a second representation for zero. Fast parallel prefix realization of such adders exist with (3 + 2[log nl) ΔG latency, where AG denotes the delay of a simple 2-input gate. Similarly, modulo-(2^n — 3) adders with excess-modulo representations of residues in {0,1,2} has been recently proposed with (4 + 2[log n|) ΔG latency. It has been shown that such double representation of residues does not jeopardize the subsequent RNS operations. To approach larger dynamic ranges, while keeping the channel widths (i.e., n) as low as possible, fast modulo- (2^n - 5 ) adders could be quite useful. That s how we are motivated to explore the design and implementation of such adders with the goal of achieving the same latency of ( 4 + 2[log n|) ΔG. The proposed scheme is basically the same as that of the aforementioned modulo-(2^n - 3 ) adders. However, there are particular non-trivial challenges to be overcome. The proposed scheme is analyzed for latency and area measures, which are confirmed via circuit synthesis by Synopsis Design Compiler.