Title of article
A Low-Power Hierarchical FinFET-Based SRAM
Author/Authors
maabi, somayeh shahid beheshti university - faculty of computer science and engineering, ايران , sayyah ensan, sina sharif university of technology - department of computer engineering, ايران , moaiyeri, mohammad hossein shahid beheshti university - faculty of electrical engineering, ايران , hessabi, shaahin sharif university of technology - department of computer engineering, ايران
From page
54
To page
60
Abstract
In this paper, a low-power energy-efficient hierarchical SRAM design capable of working in near-threshold region is proposed. The proposed method enhances the noise margin using an extra circuitry, while restricting the hardware redundancy by sharing the additional circuitry between each two SRAM cells in a hierarchical style. The results of simulating the FinFET-based SRAM cells using Synopsys HSPICE at 10nm technology node indicate that the proposed design reduces, on average, the power-delay product, read and write delays by 14.34%, 2.37% and 8.54%, respectively, and significantly improves the static noise margins even in the presence of major process variations.
Keywords
Static Random Access Memory (SRAM) , Multiport Memories , Low , Power Design , Static Noise Margin (SNM) , FinFET , Nanoelectronics
Journal title
The CSI Journal on Computer Science and Engineering (JCSE)
Journal title
The CSI Journal on Computer Science and Engineering (JCSE)
Record number
2549055
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