Gate Leakage Aware Optimal Design of Modified Hybrid Nanoscale MOSFET and Its Application to Logic Circuits

With the explosive growth in portable computing and wireless communication during last few years, power dissipation has become critical issue. Under such condition gate leakage has been recognized as a dominant component of power dissipation. This work proposes a modified hybrid MOSFET (MHMOS) i.e. gate-to-source/drain non- overlap MOSFET in combination with high-k layer/interfacial oxide as gate stack to reduce the gate leakage current. The extended S/D in the non-overlap region is induced by fringing gate electric field through high-k dielectric and SiO2 dual spacer. Compact analytical model and Sentaurus simulation have been used to study the gate leakage behaviour of MHMOS. A good agreement is observed between analytical and Sentaurus simulation results. It is found that MHMOS structure has reduced the gate leakage current to great extent as compared to conventional overlapped MOSFET structure. Further, degradation in drive current caused by the utilization of high-k gate dielectric has been improved by the use of dual spacer.