A DPA Resistant FPGA Implementation of AES Cryptosystem with Very Low Hardware Overhead

Differential Power Analysis (DPA) implies measuring the supply current of a cipher-circuit in an attempt to uncover part of a cipher key. Cryptographic security gets compromised if the current waveforms obtained correlate with those from a hypothetical power model of the circuit. During last years, there has been a large amount of work done dealing with the algorithmic and architectural aspects of cryptographic schemes implemented on FPGAs.However, there are only a few articles that assess their vulnerability to such attacks which, in practice, pose far a greater danger than algorithmic attacks. This paper first demonstrates the vulnerability of the Advanced Encryption Standard Algorithm (AES) implemented on a FPGA and then presents a novel approach for implementation of the AES algorithm which provides a significantly improved strength against differential power analysis with a minimal additional hardware overhead. The efficiency of the proposed technique was verified by practical results obtained from real implementation on a Xilinx Spartan-II FPGA.