A TECHNIQUE FOR DESIGNING VARIATION RESILIENT SUBTHRESHOLD SRAM CELL

This paper presents a technique for designing a variability aware subthreshold SRAM cell. The architecture of the proposed cell is identical to the standard read-decoupled 8-transistor (RD8T) SRAM cell with an exception that the access FETS are replaced with transmission gates (TGs). In this work, different design metrics are assessed and compared with RD8T SRAM cell. The proposed design offers 2.14× and 1.75× improvement in TRA (read access time) and TWA (write access time) respectively compared with RD8T. It proves its robustness against process variations by featuring narrower spread in TRA distribution (2.35×) and TWA distribution (3.79×) compared with RD8T. The proposed bitcell offers 1.16× higher read current (IREAD) and 1.64× lower bitline leakage current (ILEAK) respectively compared with RD8T. It also shows its robustness by offering 1.34× (1.58×) tighter spread in IREAD (ILEAK) compared with RD8T. It exhibits 1.42× larger IREAD to ILEAK ratio. It shows 2.2× higher frequency at 250 mV with read bitline capacitance of 10 fF. Besides, the proposed bitcell achieves same read stability and write-ability as that of RD8T at the cost of 3 extra transistors. The leakage power of the proposed design is close to that of RD8T.