Low Settling Time All Digital DLL for VHF Application

Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) are commonly used as a synthesizer or clock and data recovery circuit in most of the communication systems. In this paper, a new DLL is designed based on PRP conjugate gradient algorithm. The proposed DLL do not need any phase frequency detector, charge pump and loop filters, hence it can contribute better jitter performance and higher speed in comparison with conventional DLLs. In this design, PRP conjugate gradient algorithm is used to optimize the delay amount of each delay cells therefore helps the DLL to lock more accurately and quickly compared with gradient algorithm. In addition, for applying the PRP conjugate gradient algorithm a digital signal processor is used in the proposed architecture. To show the accuracy of the proposed structure’s operation, simulation has been done for 15 delay cells and fREF is chosen 14MHz to have output frequency 14×15=210MHz. fOUT=210 MHz is one of the channels in Iran VHF frequency band. As shown with simulation, the proposed architecture has a locking time of approximately 286nsec which is equal to 4 clock cycles of the reference clock.