Fault Tolerant Design of QCA Binary Wire

Dependability of a circuit is among the most important issues in the design process and reliability concerns are associated with the digital system design. A fault tolerant system should have the ability to detect, locate and correct the error and recover the system to normal operational conditions. It is more important to use fault tolerant gates in nano scale digital circuits because by decreasing the device dimensions the influence of external factors and therefore the probability of fault occurrence will increase. Since the binary wire is an essential part of digital systems and especially QCA (Quantum Cellular Automata) circuits, a redundancy based fault tolerant technique is presented in this paper to improve the fault tolerance of this part. The efficiency of this method is evaluated by MATLAB software. Results show that the fault tolerance of binary wire will significantly increase by using the proposed method. The hardware redundancy of this method is about 100% which is much less than TMR (Triple Module Redundancy) methods by more than 200% redundancy.