IMPLEMENTATION OF MULTIRATE TECHNIQUE IN WIRLESS APPLICATION USING FPGA

Multirate filter is one of the main parts that determining the receiveing quality in wireless communication. Wireless applications including ETSI DVB-T/H digital terrestrial television transmission and IEEE network standards such as 802.11 (“WiFi”), 802.16 (“WiMAX”) have high quality data acquisition and storage system requirements which increasingly take advantage using multirate techniques to avoid the use of expensive anti-aliasing analogue filters and to handle efficiently signal of different bandwidths which require different sampling frequencies. So, the present work deals with the design and implementation of multistage distributed arithmetic FIR filter with efficient cost of multiplication and storage requirement. Previous work concerning the implementation of filter is either using special programmable devices or DSP processors. Some of these works used the FPGA based architectures to implement filter in single stage but with high cost and complex design to implement. The designed arrangements are simulated and implemented using VHDL based software on Virtex-II FPGA chip. High signal resolution and large dynamic range are the main features achieved in the work.