A High-Gain Low Noise Amplifier for RFID Front-Ends Reader

A high gain CMOS Low Noise Amplifier (LNA) for 866 MHz RFID reader has been proposed and simulated in 0.18 μm CMOS technology. A new energy efficient technique along with the current bleeding PMOS devices has been used to reduce the leakage power of the RF signal and increase the gain of the proposed LNA design. Furthermore, the folded cascode with a combination of the partial source degeneration (PSD) is improved; and the current and boosting inductor are reused to enhance the gain and linearity of the proposed design. The simulation results show that the proposed LNA design outperforms the conventional fold cascode LNA in terms of gain (S21) and Noise Figure (NF). The proposed LNA achieves a forward gain of 24.8 dB with a NF of 0.38 dB with 10.6mW drawn from a 1.2V source supply; and a high linearity Input Third-Order Intercept Point (IIP3) of -3dBm.