Bit-Parallel ECC Coprocessor resistant to Differential Power Analysis Attacks in GF(2m)

Elliptic curve cryptography (ECC) is one of the most popular public key systems in recent years due to its both high security and low resource consumption. Thus, ECC is more appropriate for Internet applications of Things, which are mainly involved with limited resources. However, non-invasive side channel attacks (SCAs) are considered a major threat to ECC systems. In this paper, we design a processor for the ECC in the binary eld, resistant to Di erential Power Attacks (DPA). The main operations in this architecture are randomized Montgomery multiplication and division units, which make it impossible to create di erential power attacks by involving a random number in the calculation process. The goal is to accelerate the operation by opening the loops in the Montgomery randomized multiplication/division units, and accordingly, a bit-parallel design instead of bit-serial design. The results show that, despite the complexity of the logic in the two/three-bit processing versions, the speed is signi cantly improved by accepting a slight increase in the area resource. Further, our design is exible wherein the top-level module, depending on the area-speed trade-o , a variety of multiplier and divisor units can be selected. The FPGA evaluations show that in terms of Time Slice metric, the 2-bit divider/3-bit multiplier version of our architecture leads to a 40% improvement over the best previous work. Further, by duplicating the divider and multiplier modules along with the bit-parallel architecture this gain can reach to 50%. In terms of operation speed, our design versions are faster than previous work by a factor of 1.87 and 3.29. Furthermore, ASIC evaluations in terms of the Time Area metric, indicate that deploying a 2-bit multiplier leads to a 19% gain relative to previous well-known work. Moreover, duplication of modules along with bit-paralleling ampli es the overall gain up to 36%.