Reconfigurable VBSME Architecture Using RBSAD

This paper presents an architecture which is capable of processing variable block size motion estimation (VBSME) and which is able to apply pixel precision reduction techniques in a reconfigurable way. The design has been carried out by using online arithmetic, which allows to process all motion vectors of a block in just one iteration. The system has been implemented on FPGA and just requires 7724 slices, reaching a performance of 55 4CIF frames per second (fps) in full precision and of 72 with 4 bit precision. Results for different search areas 31×31, 32×32, and 46×46 are presented. Using 4bit precision real time processing for HDTVp is achieved. Thanks to the reduced cost and high performance, this architecture is perfect for mobile devices.