CMOS design of a multi-input analog multiplier and divider circuit

This paper proposes a CMOS current-mode multi-input analog multiplier and divider circuit based on a new method. Exponential and logarithmic functions are employed to realize the circuit which is used in neural network and fuzzy integrated systems. The major advantages of this multiplier are ability of having multi-input signals,and low Total Harmonic Distortion (THD). The circuit is designed and simulated using MATLAB software and HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35μm standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 0.9% and a THD of 0.42% in 1MHz. Moreover,the maximum power consumption of the circuit is found to be 0.89mW.