New Multiply-Accumulate Circuits Based on Variable Latency Speculative Architectures with Asynchronous Data Paths

This paper proposes the Variable Latency Speculative (VLS) Multiply-Accumulate (MAC) architectures. The proposed VLS architectures, unlike conventional MAC with fixed latencies, consists of two short and long data paths and a circuit is used to select a suitable path with minimum overhead. Two methods are considered to design the proposed VLS MAC. The first one considers the general structure of the VLS MAC with integrating the result vectors of multiplier with the accumulator, and the second method uses a novel VLS 4:2 compressor design. To investigate the proposed VLS MACs performance, all architectures have been synthesized using a CMOS 90 nm technology library, for operand lengths 8, 16 and 32 bits. Obtained results show that the proposed MAC architectures provide a variety of trade-offs in the power-delay-area space that outperform the existing designs that use only the integration technique. Moreover, the VLS MAC with the proposed VLS 4:2 compressor, in the short data path, has a delay equal to MAC with previously proposed approximate 4:2 compressor with an error recovery module. In comparison to MAC with the approximate 4:2 compressor, on average, the VLS MAC with the proposed VLS 4:2 compressor resulted in 11.26% and 13.59% lower area and power consumption.