An Area Efficient Low Dropout Voltage Regulator With Improved Transient Response for Hearing-aid Applications

This paper presents a low dropout voltage regulator, with the specifications suitable for hearing aid devices. The proposed LDO occupies very less area on chip and provides an excellent transient response. A novel voltage spike suppressor block is employed in the LDO architecture which reduces undershoot and overshoot of the output voltage during the abrupt load transition. It introduces a secondary negative feedback loop whose delay is lesser than the main loop and also steers the quiescent current to output node when required. This not only improves overall current efficiency but also reduces the on chip capacitance. The proposed LDO is laid out in 180 nm standard CMOS technology and post layout simulations are carried out. The LDO produces 0.9 V output when a minimum supply voltage of 1 V is applied. A maximum load of 0.5 mA can be driven by the regulator. The LDO exhibits 4.4 mV/V and 800 μV/mA line and load regulations respectively. When subjected to a step load change, an undershoot of 20.34 mV and an overshoot of 30.28 mV are recorded. For proper operation of the LDO, it requires only 4.5 pF on-chip capacitance.