An Improved Structure and Analysis of Asymmetrical Spacer Nanowire Tunnel Field Effect Transistor

This paper presents a novel design and analysis of a Low-k Source side Asymmetrical Spacer Halo doped Nanowire TFET. The utilization of high-k hafnium oxide spacer materials in TFET enhance electrostatic control and minimize short-channel effects in nanoscale devices. However, the performance of dynamic circuits suffers with higher fringe capacitance brought on by high-k spacers. Our method focuses on reducing gate capacitance by optimistic utilization of high-k spacer material. The proposed device is constructed in SILVACO TCAD software and results states that the use of Low-k material as silicon dioxide at the Source-side spacer in halo-doped nanowire TFET design results in significantly reduced gate-capacitance and intrinsic-delay. For this proposed TFET device, the circuit performance of advanced nanowire structure can improve drain current characteristics and analog characteristice.  The proposed device exhibits better performance as compared to other spacer engineering devices. As a consequence, the suggested device appears as a strong suitable device for low power digital applications.