مرکز منطقه ای اطلاع رساني علوم و فناوري - A Design Phase Directed Formal Verification Process

Title of article :

A Design Phase Directed Formal Verification Process

Author/Authors :

John A. Keane and Walter Hussak ، نويسنده ,

Issue Information :

روزنامه با شماره پیاپی سال 1999

Pages :

From page :

255

To page :

269

Keywords :

Temporal Logic , operating systems , high-level design , Verification

Journal title :

Software Quality Journal

Serial Year :

1999

Journal title :

Software Quality Journal

Record number :

292759

Link To Document :