Title of article
Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial
Author/Authors
Xiaoyan Ye and Xiaodong Yang، نويسنده , , Chung-Kuan Cheng، نويسنده , , Walter H. Ku and Robert Carragher ، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2002
Pages
16
From page
193
To page
208
Keywords
Model Order Reduction , interconnect , Inductance , Timing , deep-submicron , VLSI
Journal title
Analog Integrated Circuits and Signal Processing
Serial Year
2002
Journal title
Analog Integrated Circuits and Signal Processing
Record number
367211
Link To Document