A Fully Integrated CMOS Phase-Locked Loop with 30 MHz to 2 GHz Locking Range and ±35 ps Jitter

Chao Xu، نويسنده , , Winslow Sargeant، نويسنده , , Kenneth R. Laker and Jan Van der Spiegel ، نويسنده ,

روزنامه با شماره پیاپی سال 2003

7

91

97

Jitter , dual loop architecture , clock data recovery , phase-locked loop (PLL)

Analog Integrated Circuits and Signal Processing

2003

Analog Integrated Circuits and Signal Processing

367348