FPGA-based fully digital fast power switch fault detection and compensation for three-phase shunt active filters

This paper discusses the design, implementation, experimental validation and performances of a fully digital fast power switch fault detection and compensation for three-phase shunt active power filters. The approach introduced in this paper minimizes the time interval between the fault occurrence and its diagnosis. This paper demonstrates the possibility to detect a faulty switch of the active filter in less than 10 μs by using simultaneously a “time criterion” and a “voltage criterion”. In order to attain this fast detection time a FPGA (Field Programmable Gate Array) is used. The other feature introduced in this approach is that the control scheme used to compensate the current load harmonics and fault tolerant scheme are both programmed in only one FPGA. “FPGA in the loop” prototyping results and fully experimental results based on a real active power filter verify satisfactory performances of the proposed method.