Title of article
Observable Time Windows: Verifying High-Level Synthesis Results
Author/Authors
Reinaldo A. Bergamaschi Salil Raje ، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 1997
Pages
11
From page
40
To page
50
Abstract
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors
Journal title
IEEE Design and Test of Computers
Serial Year
1997
Journal title
IEEE Design and Test of Computers
Record number
431135
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