Title of article
Online and Offline BIST in IP-Core Design
Author/Authors
Alfredo Benso، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2001
Pages
8
From page
92
To page
99
Abstract
This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraints
Journal title
IEEE Design and Test of Computers
Serial Year
2001
Journal title
IEEE Design and Test of Computers
Record number
431360
Link To Document