Title of article
Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms
Author/Authors
Alexander Maxiaguine، نويسنده , , Swiss Federal Institute of Technology Samarjit Chakraborty، نويسنده , , National University of Singapore Simon Künzli، نويسنده , , Swiss Federal Institute of Technology Lothar Thiele، نويسنده , , Swiss Federal Institute of Technology ، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2004
Pages
10
From page
368
To page
377
Abstract
Scheduling on-chip resources using analytical techniques is becoming increasingly important in multimedia processing. This article presents an analytical framework for designing and evaluating schedulers for SoC multimedia platforms. The modeling technique subsumes standard event models used in real-time scheduling and accurately captures the variability in task execution requirements.
Journal title
IEEE Design and Test of Computers
Serial Year
2004
Journal title
IEEE Design and Test of Computers
Record number
431519
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