Title of article
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs
Author/Authors
Fernanda Gusmao de Lima Kastensmidt، نويسنده , , State University of Rio Grande do Sul Gustavo Neuberger، نويسنده , , Federal University of Rio Grande do Sul Renato Fernandes Hentschke، نويسنده , , Federal University of Rio Grande do Sul Luigi Carro، نويسنده , , Federal University of Rio Grande do Sul Ricardo Reis، نويسنده , , Federal University of Rio Grande do Sul ، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2004
Pages
11
From page
552
To page
562
Abstract
FPGAs have become prevalent in critical applications in which transient faults can seriously affect the circuitʹs operation. We present a fault tolerance technique for transient and permanent faults in SRAM-based FPGAs. This technique combines duplication with comparison (DWC) and concurrent error detection (CEO) to provide a highly reliable circuit while maintaining hardware, pin, and power overheads far lower than with classic triple-modular-redundancy techniques.
Journal title
IEEE Design and Test of Computers
Serial Year
2004
Journal title
IEEE Design and Test of Computers
Record number
431541
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